Project Description

This text describes the status of VISA – Virtualization Instruction Set Architecture, a project developed in Innovation Center localized in the Informatics Institute at UFRGS.

Virtualization mades possible to run multiple operating systems (OSs) on a single physical platform at same time, so multiple operation systems can share the physical resources.

A multicore architecture can run each guest OSs really in parallel, since the virtualization provide the isolation of multiple OSs stacks in their own Virtual Machines(VMs), so there are no data or instruction dependence. Multicore systems can improve the performance of a virtualized environment.

We have used ArchC and SystemC framework to design and simulate the new instructions of a MIPS processor description based on Intel Instructions.

Intel VTx is a hardware virtualization support that augments IA32 architecture with two new forms of CPU operation: VMX root operation and VMX non-root operation. A VMM runs in VMX root operation; it runs its guests in VMX nonroot operation, deprivileged in certain ways. Both operation forms support all four privilege levels (Figure 1), allowing a guest OS to run at its intended privilege level.

VT-x defines two new transitions: a transition from VMX root operation to VMX non-root called VMX entry, and a transition from VMX non-root operation to VMX root operation called VMX exit. Figure 1 illustrates the VM entry and VM exit.

Figure 1.VM entry and VM exit

The Virtual Machine Control Structure (VMCS) is a new data structure that manages VM entries and VM exits and processor behavior in VMX non-root operations. It contains fields corresponding to components of processor state. VM entries load the processor state from the guest state area and VM exits save the processor state to guest state area and then load processor state from the hoststate area. Figure 2 illustrates VM entry transition.

Figure 2. VM entry: a transition from VMX root operation to VMX non-root operation

The MIPS R3000 processor model, available at ArchC was extended to offer virtualization support, adding instructions and structures inspired in Intel VT-x.
A new structure named VMCS was added to this MIPS R3000 model, in accordance with Intel Virtualization Technology Specification. This structure has its reference in memory, but it is a special structure of processor.

1.struct VMCS
3.	bool active;
4.	int launch_state;
5.	set<string> VM_exit_cond_instruction;
7.	int rb[RB_MAX_REG];
8.	int pc;
10.	VMCS();
11.	void clear();	

Four new registers was modeled. Two of these registers keep the reference to active VMCS and to host VMCS. Other two inform if the VMX instructions are active and if the processor is in VMX root or VMX non-root operation mode.
2.                /*... old definitions ...*/
3.   /*new registers
4.   * RS[0]=VMX root(0) or non-root(1) modes
5.   * RS[1] = VMXON (1) or VMXOFF(0)
6.   * RS[2] = reference to active VMCS
7.   * RS[3] = referece to host VMCS */
8.     ac_regbank RS:4;  
9.           /*... old definitions ...*/
10.    ARCH_CTOR(r3000) {
11.        ac_isa("");
12.        set_endian("big"); 
13.    };

The implemented subset of Intel VT-x instructions is presented below:

2.  //virtualization instructions
3.  ac_instr<Type_I> vmclear, vmptrld, vmptrst, vmlaunch;
4.  ac_instr<Type_R> vmxon, vmxoff, vmcall, vmresume;
5.  ISA_CTOR(r3000){
6.   //Virtualization instructions
7.	vmxon.set_asm("vmxon");
8.	vmxon.set_decoder(op=0x00, func=0x3A);
10.	vmxoff.set_asm("vmxoff");
11.	vmxoff.set_decoder(op=0x00, func=0x3B);
13.	vmcall.set_asm("vmcall");
14.	vmcall.set_decoder(op=0x00, func=0x3C);
16.	vmclear.set_asm("vmclear %imm(%reg)", imm, rs);
17.	vmclear.set_decoder(op=0x3D);
19.	vmlaunch.set_asm("vmlaunch %expR4A", imm);
20.	vmlaunch.set_decoder(op=0x30);
22.	vmresume.set_asm("vmresume");
23.	vmresume.set_decoder(op=0x00, func=0x3F);
25.	vmptrld.set_asm("vmptrld %imm(%reg)", imm, rs);
26.	vmptrld.set_decoder(op=0x39);
28.	vmptrst.set_asm("vmptrst %imm(%reg)", imm, rs);
29.	vmptrst.set_decoder(op=0x38);
30.  };

Last edited May 8, 2008 at 8:22 PM by henrique, version 25


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